Accelerating Multiobjective Vlsi Cell Placement with Parallel Evolutionary/tabu Search Heuristics

Multiobjective combinatorial optimization problems in various disciplines remain to be the focus of extensive research due to their inherent hard nature and difficulty of finding near-optimal solutions. Iterative heuristics like Tabu Search (TS) and Simulated Evolution (SimE) have successfully been employed to solve a range of such optimization problems [1]. These heuristics are able to obtain high quality solutions, but for most real-life large size problems they may have huge runtime requirements. Parallelization of these heuristics is one of the adopted practical approach to achieve the solutions within acceptable runtimes. In this paper we address a hard multiobjective optimization problem namely, VLSI cell placement [2] with three possibly conflicting objectives: interconnect wirelength, power dissipation, and timing performance. Two heuristics namely, parallel tabu search (TS) and parallel simulated evolution (SimE) are presented. Fuzzy rules are used to design a multiobjective aggregate cost function. The parallel TS implementation is a based on a synchronous candidate list partitioning model, whereas the parallel SimE implementation is based on random distribution of rows to processors [3, 4]. For comparison purposes, a parallel genetic algorithm (GA) based on the island model [5], and a parallel simulated annealing (SA) based on the asynchronous multiple-Markov chain [6] are also implemented. Results of experiments on ISCAS-85/89 benchmark circuits are presented, with solution quality and speedup used as metrics for the comparative/relative evaluation of the presented heuristics.